5th RD50 - Workshop
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(Generated from database on 18-October-2004 - 5:49:38 PM)
| Analysis and simulation of Charge Collection
Efficiency in Silicon Thin Detectors M. Petaseccaa,b,*, F. Moscatellia,b,c, G.U. Pignatela,b aDIEI, University of Perugia, via G. Duranti, 93 – 06125 Perugia - Italy bINFN sez.Perugia, via Pascoli, 10 – 06100 Perugia - Italy cIMM-CNR sez. Bologna, via Gobetti, 101 – 04129 Bologna - Italy |
| Thin detectors have been proposed to investigate the possibility to limit the full depletion voltage and the leakage current of the heavy irradiated silicon devices. In this work we compare typical silicon detectors (diode with a 300 µm thick substrate) to thinned devices (20÷200 μm of thickness). In order to investigate the performances of these structures, simulations have been carried out using the ISE-TCAD DESSIS device simulator. The so called three-level mode] has been used to investigate the effects of the radiation fluence on the charge collection efficiency of thin and thick silicon structures. For each thickness, we simulate the hit of a MIP and then we calculate the current at the diode’s electrode. We consider a 7×1011 cm-3 n-doped substrate (in accord to an high resistivity substrate hypothesis); all the structures are composed of a 50 µm diode contact and a 15 μm distant guard ring. The simulated collected charge of the 300 μm diode is in agreement with the experimental results ; the simulation of thinner structures (50-100μm) shows a saturation of the number of e-h pairs collected at the diode’s electrode. These results suggest that an optimum thickness exists which can maximize detector radiation hardness and signal-to-noise ratio. In the next future we will develop a new model to simulate the radiation damage in p-doped substrates. |
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5th RD50
Workshop on Radiation hard semiconductor devices
for very high luminosity colliders, |